Art Original

International Journal of Electrical and Computer Engineering (IJECE) Vol.16, No.5, October 2026 | A chip level design of a multi-mode compressive sensing image sensor

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This paper presents the full chip-level design of a multi-mode CMOS vision sensor, emphasizing the detailed implementation of its circuit architecture. The proposed chip incorporates our previously developed photodiode sensing array together with the on-chip design of control circuitry. By embedding these building blocks, the chip enables pixel-level compressive sensing and supports dual operation modes, allowing the transmission of image data in both compressed and non-compressed formats. In either mode, the sensor is capable of capturing both scene images and difference images between consecutive video frames, operating at a frame rate of 40 fps. A 64*64 vision chip is implemented using TSMC 0.18um standard CMOS technology. \r\nIn the normal scene image mode, with compression (N-C) and without compression (N-nC), the structure consumes 36.99uW and 37.09uW, respectively. Meanwhile, in the difference scene image mode, with compression (D-C) and without compression (D-nC), it consumes 38.67uW and 38.75uW, respectively.

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Ketersediaan

Informasi Detail

Judul Seri

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No. Panggil

050

Penerbit

: International Journal of Electrical and Computer Engineering (IJECE)., 2026

Deskripsi Fisik

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Bahasa

English

ISBN/ISSN

2088-8708

Klasifikasi

050

Tipe Isi

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Tipe Media

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Tipe Pembawa

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Edisi

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Subjek

JURNAL

Info Detail Spesifik

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Pernyataan Tanggungjawab

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Versi lain/terkait

Lampiran Berkas

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